VHDL is an acronym which stands for VHSIC Hardware Description Language. VHSIC is yet another acronym which stands for Very High Speed Integrated Circuits. The language has been known to be somewhat complicated, as its title (as titles go). The acronym does have a purpose, though; it is supposed to capture the entire theme of the language, that is to describe hardware much the same way we use schematics.
To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block.
In this example the ENTITY statement declare a new component which name is latch, the PORT statement is used for the declaration of the input and output signal of the component. This component declaration can be assimilated to a function declaration in a high level language such as Pascal or C, but you can notice that a VHDL entity allow more than one output.
The second part of the description, the architecture declaration, is a description of how the component operates. The dataflow word is use as a description of the architecture, as far as you can have more then one possible architecture for the same component.